Generally, computer systems support interrupts. Interrupts are used to inform computer processors of an occurrence of irregular and exceptional events. Interrupts are usually the result of an event occurring in an external to a central processor such as from an event occurring in peripheral device. Additionally, an event could occur from an internal component that operates in an asynchronous manner. Interrupts typically require a processor to stop executing the normal instruction routine temporarily and switch to an Interrupt Service Routine (ISR), which can be stored in instruction random access memory (I-RAM), and is specifically designed to handle the interrupt and then return and resume the normal instruction routine. The interrupt latency can be defined as the time required by the processor to start executing the ISR after it senses an interrupt.
A conventional method for informing a processor of an interrupt is to apply an interrupt signal to the processor. Interrupt signals can differ from one processor to another. For example, in an Advanced RISC Machines (ARM) processor, two different types of interrupt request signals exist, namely, Fast Interrupt Request (FIQ) and Interrupt Request (IRQ). FIQ signals are generally used for interrupt events that have a high priority, such as network controllers. IRQ signals are used for interrupt events are generally used for signals with normal priority levels, such as keyboard commands.
As the interrupt can be generated in a variety of peripheral devices external to the processor, an interrupt control system is usually used for collecting interrupt signals received from a plurality of interrupt sources and sending the interrupt signals to the processor as interrupt request signals. Typically, when the processor senses the interrupt request, it responds to the request by branching to a predefined IRQ address in the I-RAM. When the processor executes the special instruction stored at the IRQ address, the processor is instructed to branch to another address where a global interrupt handling routine is stored. The global interrupt handling routine includes instructions that, when executed, cause the processor to a) access register(s) to interrogate the interrupt source, b) perform a table-look-up to find the address of the ISR that handles the interrupting event, and c) branch to the particular ISR address.
A processor can also use a vectored interrupt controller (VIC) that performs a vectored interrupt control function. Usually, addresses of the individual ISRs are stored in the VIC as interrupt vectors. The VIC collects interrupts generated in a plurality of peripheral devices and informs the processor of the interrupts. Meanwhile, the ISR address corresponding to the active interrupt is executed accordingly. When the processor receives an interrupt request signal from the VIC, that processor will issue an interrupt response by accessing the special interrupt vector address. Unlike the non-vectored interrupt, the instruction stored at the interrupt vector address instructs the processor to fetch the ISR address in the VIC that was activated. When the processor receives the requested address, the processor will construct a branch instruction using this ISR address. The processor will then execute the branch instruction which will direct the processor to the appropriate ISR.